Lint checking is also known as PLDRC (Prelayout Design Rule Checking). This is basically done on RTL to check for errors. We generally use a tool called Spyglass to perform the linting. Formal verification is a must. this is performed at various levels.This is actually done to make sure that during optimization stage the design functionality is not altered.Here, is a quick glimse.
During RTL and Synthesized netlist stage we keep RTL as Golden and Netlist as Revised . Then we perform a comparison, between them to prove that the functionality is unaltered. This is performed at different levels till final signoff. tool used: Synopsys Formality or Cadence Conformal LEC.
Ps Conformal is the signoff tool for Formal Verification. We rely on this and signoff the chip/core at different levels.
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