Limitations and Advantages with Partial Reconfiguration in FPGAs

[msdarvishi]

Hello everybody,

Can any one let me know the limitations and advantages associated with Partial Reconfiguration in FPGAs? Are there extra special limitations and advantages for Partial Reconfiguration in Xilinx Virtex FPGAs as well?

Thank you,

 

[code_slave]

It depends on the FPGA vendor and even the specific model.

You would need to refer to the specific FPGA data sheet, because even with a vendor like Xilinx there are limitations per device model.

Also it is the sheer amount of work involved, but you would know this if you followed up with some research and looked at the open-source designs using such approaches.