Limit of probe pads on a chip

[seamoss]

Hi,

I was wondering if there is a limitation of putting too many probe pads on a chip ? Is there something that one should be worried about before putting unneccessary probe pads?

Thanks!

 

[ZekeR]

Re: probe pad limitation

Probe pads take up lots of die area, so they increase the cost of the chip. If you were designing a chip for production, your boss would be angry if you had excessive probe pads.

Additionally, the probe pads do have substantial substrate capacitance (and it's usually not modeled), typically in the ballpark of 1pF. So, if you have a high frequency but high impedance signal attached to a probe pad, it might be attenuated so much that it's rendered unusable. Or, if you have a probe pad attached to a low-impedance node (such as the source of a MOSFET) while its gate is varied at high frequency, the probe pad will cause lots of current to be dumped through the MOSFET --potentially into a high impedance node, causing erratic behavior.

Hope this helps.

 

[dick_freebird]

Re: probe pad limitation

Sometimes you're better off designing in a test mux and
fewer pads, or even making certain noncritical pads (like
low frequency digital) serve as test-mode analog mux
outputs.

Making a probe pad in top metal for debug, and then a
2-mask spin to delete the metal and close passivation,
may be an economical development strategy. Especially
if you've alreasy planned in contingency jumpers in the
upper layers for an expected tweak after first pass.

Yeah, all you smart kids get first pass success, just
like the tool vendor says. Uh, huh.

Whether probe pads have to follow wirebond rules, is
up to you and your foundry. Bump pads don't. If you
go by that then a probe pad need not cost area or
periphery at all, presuming your core size is large.

 

[seamoss]

Re: probe pad limitation

thanks for your answers, but i wanted to know from a power network perspective, as most of the power network is laid in upper metal and probe pads are also laid in upper metal, I wanted to know if it can weaken the power network?

 

[dick_freebird]

Re: probe pad limitation

It could. But my power chips are paved with full density
thick metal and throw 10A. Yes, removing metal to
accommodate pads might "weaken" (increase resistance
or decrease reliable current capacity) but you can figure
that out, how much and where it hurts least.