[Library] Standard Cell Library dependt

[maulin sheth]

Hello All,

I just want to know that Standard Cell Library are specific for foundary or Company who make the design?

If I do RTL to Gate Level conversion thn....thn the netlist contain the different different standard cells....So, These standard cells are specific for what?

Thanks & Regards,
Maulin Sheth

 

[OhaAmo]

Yes. For example, a simple inverter with X1 driving size will be implemented differently in different foundries. It will effect its timing and power characterizations.
Approximately there shouldn't be huge differences but they surely exists.

 

[maulin sheth]

Thanks.
So standard cell library are foundary specific...right?
ALL EDA tools are supporting all library format which are generated by foundry?

 

[Prashanthanilm]

Hi,

Yes. The Foundry will have different libraries to design.

But the EDA tool will run on most of the libraries.

Only specific libraries need some modification or update in EDA tool

Thank you,
Prashanth M

 

[maulin sheth]

Thanks Prashanthanilm.
Actually I just want to know I have synopsys tool access..suppose I want to do something with the same library on Mentor tool...thn any issue occurred or not?
I have used those libraries in the synopsys tools without any issues...

 

[Prashanthanilm]

Maulin,

I am not sure on this.

But I think , running on the other tool will not be expected result allways.

 

[maulin sheth]

Re: [Library] Standard Cell Library dependent

Thanks Prashanthanilm.
I am not expecting any results as different different tools have different algorithms and different effort strategies. But I want to know that those libraries work on Mentor or not?

 

[Nanda San]

StdCell libraries may be foundry specific as well as company specific ..

The StdCell (gates) are designed by several companies for their own usage .. but the devices being used ( pmos/nmos transistors ) to draw the schematics & layouts eventually come from the foundry always . .

Different foundries will have different characterizations for each gate depending on the precess node.

The StdCells you see in your netlist obviously comes from the tech lib vendor.. (VIRAGE for example)