libraries for low power design (MSV)

[farzaneh_2561]

Hi everybody,
I'm trying to use MSV feature in SOC encounter. For inserting level shifters without specifying them in netlist, which library should I use? I mean the lib that contains level shifter cells. I already tried tsmc18, but its not inserting any level shifter and I guess this lib does not have any level shifter.
I really really appreciate your help.

 

[rca]

well to insert automatically the level-shifter, you need:
1- library file which contains this level-shifter, the liberty must have the power-pins.
2- CPF flow to indicate where you want to insert the level-shifter.

 

[farzaneh_2561]

yes, you are right. but my problem is that I don't know which libraries support MSV. for example I know that tsmc support low power but it doesn't contain any level shifter cell or at least I didn't find any.

 

[Yarrow]

Look into the liberty (.lib) file. Search for something like "ls*" If there are no level shifters, change the library or design your own level shifter and use that one.

Like rca said. Use CPF to specify your level shifter library and supply voltage domains. I personally dont know of a simpler way.

Designing your own level shifter and including it into your flow will take some effort if you have not done it before.

 

[rca]

Well for what I know, the 0.18um TSMC libraries are not compliant with low power flow.
At 65nm TSMC, the std-cell are low power flow compliant.

 

[farzaneh_2561]

well thank you all, for your helpful answers

 

[farzaneh_2561]

Designing your own level shifter and including it into your flow will take some effort if you have not done it before.

do you any good tutorial that I could use?

 

[Yarrow]

I do not know of any single tutorial for this purpose. What I did, I designed my own libraries (including level shifters) which were compatible with MSV design.

I used the following tools (this flow also adds the level shifters in the netlist automatically after specification in CPF):

Cadence Virtuoso: Schematic, layout
Cadence Abstract Generator: To generate the abstract views for the SOC Encounter
Virtuoso LEF Out: To generate the LEF file of the libraries (or a single level shifter if you will, then include in whatever .lef file you are using)
Encounter Library Characterizer (ELC): To generate the .lib file (an entry for the level shifter may be written manually)
Encounter RTL Compiler (RC): For the synthesis of the HDL code
Common Power Format (CPF): For controlling the power domains, level shifters and other low power stuff already at RTL level
SOC Encounter: For place and route

This flow would give you control over the libraries, level shifters and power domains from front- to back-end. The advantage is that here you are not adding stuff at the back-end and then converting back-end stuff back to the front-end to do verification (LVS).

If you wish to include a custom level shifter into your flow without adding it in the netlist you would still need to design/write a schematic, layout, abstract, .lib entry (?), .lef entry and use SOC Encounter to place and route the level shifters.

This is the only approach I know if you do not have a level shifter in your existing library. However, perhaps someone else knows of a simpler approach.