mskh744
Newbie level 5
I use leonardo spectrum for my synthesis & gate netlist analysis, preparing for ASIC implementation. I already used Modelsim to create verilog files and all of them were compiled successfully and have been tested for functionality. However, when it came to leonardo, it refuses "reg" data types and report them as errors, inspite of being legal to use them in Modelsim.. so do anybody have a suggestion for this problem (knowing that I already replaced all reg data types except the memory part, because its irreplaceable )
another problem came when I read some files successfully (no errors), and commanded to write them as verilog files, the log window said it has been written successfull, but when I go to the destination of created file, I cannot find it.. tried to write 100 times but with null output every time.
One last error pops-up a lot: "symbol 'module_name' was already defined ".. modelsim reports no error similar to this one, but yet leonardo does.
Thanks in advance
another problem came when I read some files successfully (no errors), and commanded to write them as verilog files, the log window said it has been written successfull, but when I go to the destination of created file, I cannot find it.. tried to write 100 times but with null output every time.
One last error pops-up a lot: "symbol 'module_name' was already defined ".. modelsim reports no error similar to this one, but yet leonardo does.
Thanks in advance