Legal net Ivalue error in module call

[goldfingermafia]

Legal net Ivalue error

I keep getting a net Ivalue error in my program. Can someone please help me figure this out, i think it has something to do with the face that data_cpu is not fully populated until 200ns. please help me find a solution to this. If anyone wants the files please email me at goldfingermafia@yahoo.com. Thank you

definition:
input wr;
input [7:0]BE;
input [3:0]address;
inout [63:0]data;
inout[31:0]data_out;
output [3:0]address_out;
output [3:0]be_out;

reg [3:0]be_out;
reg [3:0]address_out;
reg [63:0]data_in;
reg [63:0]data_hold;
reg [63:0]data_cpu=0;
reg [31:0]data_out_in;
reg [63:0]data_out_hold;
reg [63:0]data_decide;


module call:
bitR64 R64(
.wr(wr),.clk(clk),.address(address[3:0]),.BE(BE[7:0]),.data_out(data_out_hold[31:0]),
.address_out(address_out_r[3:0]),.data_cpu(data_cpu[63:0]),.be_out(be_out_r[3:0])
);

module bitR64 R64:
module bitR64(wr,clk,address,BE,data_out,address_out,data_cpu,be_out,
);
//inputs
input wr,clk;
input [3:0]address;
input [7:0]BE;
input [31:0]data_out; // input of read modual
//output
output [3:0]address_out;
output [63:0]data_cpu; //output to CPU
output [3:0]be_out;
//registers
reg [3:0]be_out;
reg [3:0]address_out;
reg [15:0]delay=0;
reg [63:0]data;
reg [63:0]data_cpu=0;




always@(posedge clk)
begin
delay=delay+clk;
end

//set address to address +1 to read data.
always@(negedge clk)
begin
if(~wr)
begin
begin
if(delay < 100)
begin
assign be_out[3:0]=BE[3:0];//output BE, only low
assign data[31:0]=data_out[31:0];
assign address_out[3:0]=address[3:0];//address output
end
else
begin
assign be_out[3:0]=BE[7:4];
assign data[63:32]=data_out[31:0];
if(delay <101)
begin
assign address_out[3:0]=address_out[3:0]+1;//limits so that address only incresses one time
end
end
end
end
end
always@(posedge clk)
begin
if(~wr)
begin
if(delay>101)
begin
assign data_cpu=data;
end
emd
end

endmodule