I can't comment exactly without knowing the details of your design/mems. But the premise behind doing LEC between pre and post scan inserted netlists is to confirm that the functional design between the 2 netlists are functionally the same. Therefore all scan paths should be turned off.
Any scan control pins, including inputs to mems, should be controlled by top level scan control signals which you should tie off (de-asserted). If the memory scan input pins for some reason are not connected then they should be tied off at the mem instantiation level if they are causing the LEC to fail.
I use the phrase top level, but the scan control pins don't necessarily need to come from primary inputs of the chip. They could come from a DFT instantiated block that provides the scan control signals, it depends on how the DFT logic was implemented.