How to measure leakage current of a simple CMOS inverter using hspice? Is there any other estimation method by which we can compare the calculates value with hspice value? I tried by making the transistors OFF and then measured Idd, Is and Ig. Is is right? Please explain. Thank you.
It would surprise me greatly if the MOS model leakages
were at all accurate.
In the case that there is any significant D-S leakage
the logic high/low level will no longer be ideal and this
will enhance leakages further.
You could simply wire up a large chain, take the IDD
value and divide by N; this ought to roll up all the
factors you mention, and then some. To the degree
of accuracy inherent in the models, at least. Which
is always to be questioned.