Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Leakage measurement using Hspice

Status
Not open for further replies.

nareshec

Newbie level 4
Joined
Sep 16, 2009
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,320
How to measure leakage current of a simple CMOS inverter using hspice? Is there any other estimation method by which we can compare the calculates value with hspice value? I tried by making the transistors OFF and then measured Idd, Is and Ig. Is is right? Please explain. Thank you.
 

It would surprise me greatly if the MOS model leakages
were at all accurate.

In the case that there is any significant D-S leakage
the logic high/low level will no longer be ideal and this
will enhance leakages further.

You could simply wire up a large chain, take the IDD
value and divide by N; this ought to roll up all the
factors you mention, and then some. To the degree
of accuracy inherent in the models, at least. Which
is always to be questioned.
 
hspice or synopsys some tool ,
as I remember have other tool like hsimplus or others ..

can use script file to monitor leakage current

Vgs Id ..etc
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top