Leakage Current in hspice

[electronics20]

Dear researchers
I am redesigning a conventional SRAM 6T. How to measure leakage current in SRAM by HSIPCE? I mean that I need required code to apply to HSPICE environment.
Many Thanks

 

[dick_freebird]

Well, I'm not about to invent code for you. But you should
be able to identify devices in your circuit which express the
leakage (like, say, the two PMOS of the cross coupled pair
and the two bit-switch devices, are the only paths from
VDD to VSS in the core cell, so sum them (ID(OP) and
multiply). Now these currents may not be well modeled,
in I-V detail across the operating-point range by whoever
did the work, but that's another issue.

You could put a trivial sense resistor in the bit-cell ground
leg (if sense amp and write drivers are sourcing current)
or VDD (if sinking) and eliminate the need for arithmetic.
Provided you are careful about not double counting things.
Undestanding the operation will take care of that I expect.

The other major blocks, the sense amp, write drivers, self-
timing and so on, you could treat similarly.

 

[electronics20]

Thanks, would u mind more explaining about sense resistor and this sentence: " you are careful about not double counting things".

 

[electronics20]

Ok, I got it. I have another question.
How to measure and determine "Gate oxide leakage current" and Subthreshold leakage current" separately in SRAM cell 6T by HSPICE?
Many Thanks in advance

 

[erikl]

Gate oxide leakage current: Measure/print/plot gate current
Subthreshold leakage current: Measure drain current in subthreshold mode (MOSFET off)