LDO small signal problem

[max0412]

What am I doing wrong? When I use a buffer to drive the pass FET (NPN or N-FET) I get a correctly generated bode plot. When I remove the buffer and configure the EA to directly drive the pass FET the bode plot is garbage.

I don’t need a buffer to drive the FET. The output is from 2 to 15 mA (5.1V) there is OCP which will shutdown power to the LDO when it exceeds 12mA.Input 5.2 to 6V.

Schematic

Output

 

[LvW]

What am I doing wrong? When I use a buffer to drive the pass FET (NPN or N-FET) I get a correctly generated bode plot. When I remove the buffer and configure the EA to directly drive the pass FET the bode plot is garbage

I don´t understand where and why to use a buffer ?
Two recommendations:
1.) Don´t use the LC method for ac loop gain response. Instead insert an ac source BETWEEN point FB at the positive opamp input (P) and display db(V(FB)/(V(P))
2.) Check if the bias point is OK (display it on the screen)

3.) Question: Don´t you need a capacitor across the load ?

 

[max0412]

I don´t understand where and why to use a buffer ?

I was trying different things to figure out why I couldn’t get the correct output. This is what I mean.

From Sandler.

But no I’m not using an external driver/buffer to drive the FDV304P.

Don´t use the LC method for ac loop gain response. Instead insert an ac source BETWEEN point FB at the positive opamp input (P) and display db(V(FB)/(V(P))

Your suggestion worked.Thank you.

Schematic

Output

Sorry my schematic is a bit disorganized for the reason mentioned above (trying different methods).There is an output cap there before the divider network 3.3uf C2.

 

[LvW]

Yes, I have realized the output cap. Sorry, I have overlooked it in your first schematic.
I think, your loop gain doesn´t look to bad. Any further problems ?
By the way: The method for simulating the loop gain with a series ac source works always nearly perfect, if you can find a point within the loop which you can break to insert the source WITHOUT remarkably changing the load conditions. That means: in front of a high impedance input or after a low impedance output. Very often, you can find such a point.

 

[max0412]

I think, your loop gain doesn´t look to bad

Agreed for those line and load conditions. But when I decrease the line voltage from 6V to 5.35V. I get this.

Could you recommend an app note or book that could provide guidance in compensating LDO's with an external P-FET.

I've used the LP2975 controller and following there guidelines Built a 6.2V LDO 120mA that shows no signs of instability in bench testing. This is in fact the input for the LDO schematic above. I'm trying to get the LDO above to regulate to as low a Vi -Vo diff as possible,because the LP2975 maybe several hundred feet from this Regulator (DC copper losses).

Would using the same design guide for the LP2975 be applicable here or could you recommend an alternate guide.

LP2975 Datasheet

http://www.national.com/ds.cgi/LP/LP2975.pdf

Using another LP2975 is to pricey or even other IC LDO's. I already have a reference, and an spare EA from a MCP6004 on the board. So all that's required is the Pass Fet and some passives.

MCP6004 Datasheet

http://ww1.microchip.com/downloads/en/DeviceDoc/21733h.pdf

 

[LvW]

Sorry, I have no experience with the LP2975.