saqib.shah06
Junior Member level 2
Hi everyone,
I have a question regarding the output impedance of a LDO, which I am trying to simulate in HSPICE.
It is a basic design with an error amplifier and a PMOS pass transistor. I am having the following doubt.
For any given LDO, the dominant pole lies at P= 1/RC (R = rds of the pass transistor and C=output cap ). My HPSICE simualtions confirm this. I am injecting the AC signal by breaking the feedback loop (this ahs been perfectly design - i have checked it multiple times). However when I do a .tf analysis in HSPICE, the .lis file says that my output impedance is 100milliohm. (the rds of the pass transistor is around 75 ohm). Can someone please explain this discrepancy?
btw I am using very large feedback resistors (100k each), and a current source load. The output current is around 100mA
Thanks a lot!
I have a question regarding the output impedance of a LDO, which I am trying to simulate in HSPICE.
It is a basic design with an error amplifier and a PMOS pass transistor. I am having the following doubt.
For any given LDO, the dominant pole lies at P= 1/RC (R = rds of the pass transistor and C=output cap ). My HPSICE simualtions confirm this. I am injecting the AC signal by breaking the feedback loop (this ahs been perfectly design - i have checked it multiple times). However when I do a .tf analysis in HSPICE, the .lis file says that my output impedance is 100milliohm. (the rds of the pass transistor is around 75 ohm). Can someone please explain this discrepancy?
btw I am using very large feedback resistors (100k each), and a current source load. The output current is around 100mA
Thanks a lot!