LDO output capacitor

[viviadam]

Why do we add a capacitor at the LDO output if the LDO output is going to have a huge parasitic capacitance since it is going to be the power net of several blocks?
So should we just add this estimated parasitic capacitance during simulations and stabilize the loop? Is it necessary to make another Load cap at the LDO output?

 

[KlausST]

Hi,

Is this for IC (inside) design?

Klaus

 

[danadakk]

https://www.ti.com/lit/an/snva167a/snva167a.pdf page 5 in particular.


Regards, Dana.

 

[dick_freebird]

It's all about the "If".

Decoupling at the point of consumption may
be too remote, inductive/resistive-degenerated,
to stabilize the LDO. Many LDOs are more stable
with low quality caps than near-zero-ESR but
that falls apart at some point. It's even less likely
that one "client"'s decoupling can provide the
step-load current to meet load-step regulation
at another remote location.

Designers aren't going to model a complex PDN
in the course of design; if you're lucky the output
cap impact on stability is characterized and
component C, ESL, ESR bounds provided for board
design.