LDO Feedback Resistor LVS error

[dhruvabedre]

Hi all,

I am using Synopsys Galaxy Custom Designer for layout editing & IC validator for verification.

I was doing layout for feedback resistor of LDO, but I am getting the LVS error which is

"Schematic block performs series or path merging but contains no power or ground nets."

"Layout block performs series or path merging but contains no power or ground nets."

Please help me with this & also I have attached the screenshot.

 

[Amy25]

hi,

Check for your bulk connections. and I don't see the vss in layout connected anywhere