LDO design

[Purushotham S]

Hello, I am designing an LDO. I am using two stage opam as error amplifier. I am connecting the output of opam to the gate of pass transistor. How to calculate load cap and Slew rate for opam calculation,l

 

[KlausST]

Hi,

there are many ways to connect a FET to an amplifier.
* N-Ch, P-Ch
* as voltage follower
* as current source
* and so on

--> show your schematic. If you did not draw yet, then it´s high time, at least for a sketch.

***
A design starts with requirements and specifications. Then to find a suitable solution. There are plenty of LDO designs around. Many come with design notes, examples, calculations...
Just do an internet search, read through a couple of them. Choos the document that suits you most.Try/calculate/simulate on your own. And on questions, show what you have done so far and refer to the document you used.

Klaus

 

[D.A.(Tony)Stewart]

If you designed it then you ought to know how to compute the gain , BW and Rout of the design with various conditions with negative feedback. Then you can determine load range and load sensitivity on stability. A Bode Plot is used to measure phase margin and plot how load R and X(f) affects phase margin. A partial derivative may yield the sensitivity of each part in your gain equation. When using a FET bypass transistor, there may be unstable zones with too small and too large a load capacitance . An internal load Cap and internal RC compensation in a small FET LDO serves to extend gain and phase margin while reducing step load peak errors.

Critical specs;
Vin range
Iout range
PSRR @ 10 MHz = GBW/10 MHz
Compensation RC pole
Minimum load C

also:
Step load error
Thermal error
Input regulation error
Output noise figure.

 

[Purushotham S]

If you designed it then you ought to know how to compute the gain , BW and Rout of the design with various conditions with negative feedback. Then you can determine load range and load sensitivity on stability. A Bode Plot is used to measure phase margin and plot how load R and X(f) affects phase margin. A partial derivative may yield the sensitivity of each part in your gain equation. When using a FET bypass transistor, there may be unstable zones with too small and too large a load capacitance . An internal load Cap and internal RC compensation in a small FET LDO serves to extend gain and phase margin while reducing step load peak errors.

Critical specs;
Vin range
Iout range
PSRR @ 10 MHz = GBW/10 MHz
Compensation RC pole
Minimum load C

also:
Step load error
Thermal error
Input regulation error
Output noise figure.

Hello Here are my specs
I have been asked to design a LDO. Vin range : 1.62-1.92V, VOUT: 1.4V (3 sigma), Current range: 100u-100mA in 100nsec, Vref: 0.8V( 3 percent +/_), CL=1uF, BW of the Amplifier=5Mhz, gain=6000v/v . I took all these specs and simulated in cadence in all the possible corner with. Now im intrested in designing in two stage amplifier but i want to know the CL, slew rate for the cap.

 

[dick_freebird]

Op amps are too weak, generally speaking, to drive a
usefully-large pass FET. So-doing will give you a huge
Miller pole (FET Cgd and op amp linear drive) and poor
HF PSRR & step-load dynamics.

 

[D.A.(Tony)Stewart]

You should do some research and find the excellent publication on this cascode FET design.
OA's are too slow.

 

[Purushotham S]

You should do some research and find the excellent publication on this cascode FET design.
OA's are too slow.

shall i increase the gain to 10000? and how to decide a two stage opam for that mosfet, Any resources?

 

[D.A.(Tony)Stewart]

shall i increase the gain to 10000? and how to decide a two stage opam for that mosfet, Any resources?

Ignore my OA comment and read the rest again, then take action. It took me 1 minute. Prefer to note Researchgate.com

 

[Purushotham S]

Ignore my OA comment and read the rest again, then take action. It took me 1 minute. Prefer to note Researchgate.com

I think I am beginner in this field, can u please let me know any good resources for it. I would be so helpful

 

[dick_freebird]

I would begin with figuring out the op amp output stage,
which must swing all the way to VIN if you want control of
low-load Vout / Iout (else, go to a Class B output with a
sink FET).

The PMOS output device contributes a widely varying
(w/ Zout, Iout) stage-gain - Zout being not just resistive
but also a pole whose frequency swings wide as well).
You may need some smarts about compensation to
track out that variation as best you can. Like a zero-
resistor (as MOSFET) whose Ron is made to vary with
the state of MPout. But then there's the variation in -that-.

Your loop compensation has to comprise the "op amp"
gain core, any buffer gain and delay and the pass FET.
Working back-to-front is the only way that's ever worked
for me (a front-to-back approach will make a U-turn or
more than one as you add "stuff" along the lineup).

 

[D.A.(Tony)Stewart]

I think I am beginner in this field, can u please let me know any good resources for it. I would be so helpful

There are so many papers online. This is what I wanted you to learn how easy it is to find them. But it seems you did not try. Why is that?

All opam assignment2_main

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