ldmos with non-epi proces

[ljy4468]

Hi all
I have seen ldmos which is integrated on well instead of bl/epi layer.

I know parasitic pnp is easy to operate because of high base resistance.
Then is there another drawback with non-epi wafer?

 

[dick_freebird]

If the LDMOS body is the handle wafer (as is the case with
LDMOS grafted onto cheapest CMOS base processes) then
being on non-epi substrates makes the body tie weaker and
needs denser contacting to keep the parasitic NPN quiet.
High voltage devices will make the epi Xj requirement pretty
deep so this may not be that big a deal in the end, but you
need to know. And what works, there, will depend a lot on
things like max local die temp and max drain dV/dt.