layout versus schematic verification

atlaakreddy said:

what is the difference between the spice netlist,lvs.v,schematic netlist?please expalin withe detail?

what is the formate of spicenetlist, normal netlist, schematicnetlist, lvs.v?

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atlaakreddy said:

give one example of schematic netlist and normal netlist

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oratie said:

As a simple example:
1. after place'n'route you have gate-level netlist (.v verilog), which contains std. cells and wires between them).
2. also, you should have spice (transistor-level) netlist (.sp, .cdl or other extensions), which contains transistors and wires for each of you std. cells.
3. you should convert gate-level netlist into spice-like netlist and merge it with std. cell transistor-netlist.
4. the LVS tool extracts transistor netlist from layout (GDSII) and writes it into spice-like netlist .
5. the LVS tool compares your merged tran-level netlist with extracted tran-level netlist.

The extensions of netlist files may vary and depend on LVS tools.

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atlaakreddy said:

normal netlist means .v

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you can make LVS pass using gate-level netlist, no need to do spice vs spice

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oratie said:

Only in case the hirearchy fully match in schematic and layout. Still, standard signoff (foundry recommended) LVS is transistor-level comparison.

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You can do verilog vs spice.

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