i m having a problem while making layout, i m using N+ poly resisitor NMOS capacitor in UMC 180nm technology. i m not able to under how to connect in my layout,can u give snapshot of some layout so that i can see that.I m attaching snapshot of two stage opamp in which i m using res. and capacitor...... plz reply as soon as possible.
And I'm not able to understand your problem. I guess you use pcells from the UMC PDK for your resistor and caps, so what's the pb? Connect them like any other device! By metal1, preferrably.
BTW, why would you want such huge caps, and why a cap (C1) at the output?
whatever is the layout for N+ poly resistor and nmos capacitor, i m not able to connect it with terminals like vss or gnd. if u can hellp plz help me..
I really cannot see your problem. Could you describe it better? Why can't you connect the 3rd terminal to VSS ? Could you possibly show a clipping of your layout to better describe the pb?
i m having a problem while making layout, i m using N+ poly resisitor NMOS capacitor in UMC 180nm technology. i m not able to under how to connect in my layout,can u give snapshot of some layout so that i can see that.I m attaching snapshot of two stage opamp in which i m using res. and capacitor...... plz reply as soon as possible.