hello i want to ask,if i design the layout pcb like a picture, if the transistor input that I rounded was sharpened like in the picture what would affect the matching impedance?
Not sure how you arrived at the TL matching network. It looks considerably different from reference design in CGH40006S datasheet. Consider that the MLIN model doesn't cover the discontinuities at the line ends.
The worst point of your layout is however the ground connection of bypass capacitors and transistors. I'm sure that the demonstration PCB uses multiple small vias below the QFN exposed pads. The different ground connection of capacitors is obvious on the photo.
Which simulation results? Did you simulate the actual geometry, e.g. with ADS Momentum? If not, can you know how your PCB behaves? The demonstration board is assuming 35 pH source inductance for the transistor, can be hardly achieved with a single via.
I believe that the simulation results are good. But the simulation circuit is far from representing your PCB design. It has huge parasitic inductances due to insufficient ground connections. And the matching transmission line structures need more accurate modelling than by simple MLIN segments.