Layout of MOS chopper switches

[spectrallypure]

Hi all! Does anybody know any reference dealing with how to properly layout the chopper switches in a chopped amplifier? I am talking about, for example, of the choppers S1-S4 in the figure below:

**broken link removed**

The de-facto analog layout book (Hastings) does not deal with this topic. I've read everywhere that the layout of these switches is critical, yet I haven't found any practical details/examples on how to actually do it... :\

Thanks in advance for any help!

Cheers,

Jorge.

PS. In case someone wonders, for my choppers I am using NMOS transistors (the common-mode voltage of the signals to chop is very close to ground!), and I am adding shorted dummies (of half the width) at the sides of each switch for reducing charge-injection errors So basically I would like to know how to actually layout all these guys together!

 

[Braski]

Chopper switches are critical from the charge injection and residual offset point of view.
First, symmetry is critical. You should maintain an exact symmetry between each path of the chopper switches. Second, you should minimize parasitic capacitance from drain to gate. You can use a shielding intermediate metal layer connected to ground to reduce the parasitic capacitance. Third, avoid routing clock phases near to sensitive signal paths, especially in an asymmetryc shape. Otherwise, non-simmetric parasitics will cause non-simmetric charge injection -> residual offset.