Layout of current-output current-steering DAC

[melkord]

Hi,
Any tips to reduce the area of current-output current-steering DAC? or maybe better floorplan?
I feel that the current mirror arrays takes so much space but not sure how to make it better.

Here is my layout:

 

[AMS012]

Trying to achieve better matching across the current sources usually ends up with more area as you try to match each and every small bit of routing across the array. That's why if you see papers on high precision data converters (say more than 12bits), you will see them quoting a few mm2 of active area. Not sure what's the accuracy and area for your layout. I would suggest you to compare it with a few good IEEE journals to see where you stand. Other than that, you could probably try to merge the multipliers into fingers which might reduce a bit of the area for you.

 

[dick_freebird]

The dimensions of "better" are your trade-space.

It might be that you want to "goalpost" the design space like one version that puts area first, and one that puts accuracy first, to see whether your small one meets sensible performance specs and whether the accurate one fits sensibly in a SoC floor plan. Nuances are often unknown until silicon hits the bench.

 

[sutapanaki]

There is a paper by Klaas Bult in the JSSC, maybe from 2009, don't remember exactly, on optimizing the area of current steering dac based on accuracy, mainly INL/DNL. Worth checking it up.

 

[melkord]

There is a paper by Klaas Bult in the JSSC, maybe from 2009, don't remember exactly, on optimizing the area of current steering dac based on accuracy, mainly INL/DNL. Worth checking it up.

Hi,
I have been looking for the paper you meant every now and then, but unfortunately I still cannot find it.
Could you give a more specific info about the paper?
here is the list of his publication.
I found this, but I am not sure this is what you were referring.

 

[sutapanaki]

The paper that you linked in your post is also a good one. The one I meant is under reference #2 from 12/1998 in JSSC

A 10-b, 500-MSample/s CMOS DAC in 0.6 mm