The only passive devices that can be "nearer the bond pad" in the vertical sense are the MIM capacitor and Metal Inductor. Depending on how close is close, these devices would not care. Resistors, PIS capacitors, MOSFETs, BIPOLARs, varactors, etc are all close to the silicon surface. At technologies < 0.22um, they are at and below the silicon surface as a result of using Shallow Trench Isolation (STI).
For a standard foundry, a rule of thumb is roughly 1um between metal layers. So a 4 layer metal process means that the top metal is 4um vertically away from the silicon surface where most of the active components are built (but this is a very rough approximation).
However in multi layer technologies, it is possible to place active circuitry under the bond pad, when the bond pad is so far away vertically.
So for a 6 layer metal process, the top layer is close to 6um away and will not affect circuitry at the silicon surface. In reality it is closer to 5um but this may still be good enough margin if the circuitry below the pads is not highly sensitive to matching (layout).