**broken link removed** is a good starter on the layout of a capacitor. Make sure you're using the right layers for your own process. Also, you should take a look to see if there is a capacitor layout in the libraries provided by your foundry.
It depends on your design. If you want a smaller size, you will need lager unit capacitance value, which is determined by technology process. If your design doesn't care for the precision and parasitic of capacitors, you may use MOS capacitors.
I think the best solution is to use the layout of the capacitor given by the technology. When you have a big value you can divise the capacitor into 2 or 3 sub-capacitors.
The best way to do a cap for your application will be ever technology dependent, and the more efficient one will come out from the list of availble components in your process... and that's it...
Then you can start discussing which is the most efficent layout technique to use for drawing it... if your circuit is not needing such a critical absolute value, you can just have a single big/huge cap. If not it will be (always) a good technique to split it down in smaller caps and use dummies surrounding them in order to get a better result.
Firstly u need to decide about, wher the cap will be placed if one side is vgnd then nmos, if one side is vpwr then pmos or if both sides are varying then MIM cap will be better. Hope this helps.
Well how big is the rest of the circuit? How big is a bondpad? Sometimes designers do their best to squeeze down all caps. And then somebody decides that you should have two test pins anyway. Or a huge logo...
My idea: only worry about capacitors if your chip doesn't fit in the package.
But anyway, just look in the DE manual. And find out which caps are available. normal MOS caps tend to be non linear, and have huge paracitics. Some processes have nice linear area effective poly poly caps. If you have more metal layers you could sandwich all metal layers. But in some processes the gap between metals is not a control parameter, which means that it spreads. So trade off between area linearity and spread...