Try not to do any post-processing, if possible, you may create more problems.
Most likely, your problem is caused by a mistake in the layout.
The devices are recognized from the layout by LVS tool (using seed and terminal device recognition layers).
There are rules for 2-terminal n-well resistor, and rules for 3-terminal resistors.
Obviously, your LVS detected 2-terminal resistors in the first case, but 3-terminal resistors in the second (wrong) case.
Try to find the layout differences, find what layer and shape changes did you do, and resolve it at the layout level.
Max