I see many wafers with substantial gradient in VT and other
attributes. But scaled to sensible distances the numbers
become less than the statistical mismatch floor. For example
100mV across wafer (at, say, 10cm spacing between
WAT keys) or 10mV/cm becomes 1uV/um.
Now, if you're talking a part with any kind of on-chip power
dissipation, the spacing also plays with the thermal gradient
if you are laid out longitudinal. We used to take great care
to orient pairs orthogonal to the expected thermal gradient
back when you'd design one op amp and put in a can. Of
course large, multi-heater, cell based designs make this more
of a headache. But it is worth considering in power products.