Latency trade off in IP core

[spman]

Hello,

What is the trade off of adjusting latency when implementing an IP core such as floating point with coregen?
How does latency affect the core? and where does latency have usage?

Thanks

 

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adding latency in the floating point core will result in inputs generating the corresponding outputs after a larger number of clock cycles.

Latency is a way to improve performance by pipelining a design so that each stage has less logic between registers and therefore has less delay between registers. This results in outputs for a given set of inputs showing up later by the number of additional pipeline stages. As long as the operation that is pipelined doesn't have feedback you will be able to generate output data at every clock cycle.

 

[spman]

So latency doesn't have effect on performance (clock frequency, delay, ...) of the pure floating point core. right?

 

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Latency stages are likely to improve performance due to the reduction in logic between the registers that are added.

Latency won't affect data throughput performance of the core at a given clock frequency.