Apr 18, 2014 #1 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 How can the late arriving signals be provided while doing synthesis using Design compiler so that tool understand they are late arriving signals?
How can the late arriving signals be provided while doing synthesis using Design compiler so that tool understand they are late arriving signals?
Apr 21, 2014 #2 W whizkid123 Junior Member level 2 Joined Oct 6, 2011 Messages 23 Helped 1 Reputation 2 Reaction score 3 Trophy points 1,283 Location Singapore Activity points 1,421 Hi Sun Ray, What do you mean by "late arriving signals" . Do you mean the signal arrival time is bigger at Flop Input than required time?
Hi Sun Ray, What do you mean by "late arriving signals" . Do you mean the signal arrival time is bigger at Flop Input than required time?
Apr 22, 2014 #3 R rahul.achates Banned Joined Nov 19, 2009 Messages 150 Helped 25 Reputation 120 Reaction score 56 Trophy points 1,308 Location Bangalore Activity points 0 please provide more information .... if a signal is expected to arrive late ( I am assuming your mean here is signal taking more than 1 clock cycle ), you need to define that signal as multi cycle path in your constraint file Rahul
please provide more information .... if a signal is expected to arrive late ( I am assuming your mean here is signal taking more than 1 clock cycle ), you need to define that signal as multi cycle path in your constraint file Rahul
Apr 22, 2014 #4 S sun_ray Advanced Member level 3 Joined Oct 3, 2011 Messages 772 Helped 5 Reputation 10 Reaction score 5 Trophy points 1,298 Activity points 6,828 Here the late arriving signal may not be a multi cycle signal.
Apr 23, 2014 #5 R rahul.achates Banned Joined Nov 19, 2009 Messages 150 Helped 25 Reputation 120 Reaction score 56 Trophy points 1,308 Location Bangalore Activity points 0 provide more information ... specify clearly what is late arriving signal ? rahul