Late signals during synthesis

[sun_ray]

How can the late arriving signals be provided while doing synthesis using Design compiler so that tool understand they are late arriving signals?

 

[whizkid123]

Hi Sun Ray,

What do you mean by "late arriving signals" . Do you mean the signal arrival time is bigger at Flop Input than required time?

 

[rahul.achates]

please provide more information .... if a signal is expected to arrive late ( I am assuming your mean here is signal taking more than 1 clock cycle ), you need to define that signal as multi cycle path in your constraint file

Rahul

 

[sun_ray]

Here the late arriving signal may not be a multi cycle signal.

 

[rahul.achates]

provide more information ... specify clearly what is late arriving signal ?

rahul