Latch over flip flop

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shweta.bphc

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Hi,

I know that most of the digital designs use flip flops because they are more compatible with EDA tools and timing calculations are easier with FFs. But I wanted to know if there is any situation or scenario where latch is preferred over FF?

Thank you.

regards,
Shweta
 

In FPGAs, latches are never preferred.

Only in obsolete parts do actual latches exist, e.g. Xilinx 3000 series parts. The only way to implement latches in modern parts is to have a feedback circuit built from LUTs, which can result in timing problems due to differences in placement and routing.
 

I know in ASIC design some people still use latches. Flipflops consume more power than latches as power is consumed during any toggle.
But generally the preference is to move to fully synchronous design.
 

TrickyDicky said:
I know in ASIC design some people still use latches. Flipflops consume more power than latches as power is consumed during any toggle.
But generally the preference is to move to fully synchronous design.
Click to expand...

and even then, only for very special situations like clock gating cells.
 

ThisIsNotSam said:
and even then, only for very special situations like clock gating cells.
Click to expand...

Back when I worked on ASICs if you wanted to add a latch, you had to justify that it was necessary with the rest of the ASIC team and have your constraints looked over very carefully. If you couldn't prove it was necessary you had to remove it.

The only times I've ever used latches were with some ancient asynchronous bus protocols that ran at 10 MHz that required a latch to capture the address, and had a signal called address latch enable just for that purpose.
 

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