Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

latch in verilog should use nonblocking assignment ?

Status
Not open for further replies.
O

onion2014

Member level 1
Member level 1
Joined
Mar 25, 2013
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
NY
Visit site
Activity points
1,574
hello all, i read a article about blocking and nonblocking, it says that latch should be implemented using nonblocking assignment. but i don't know what's the reason for this. can anyone explains this a bit more. thanks in advance.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top