lan91c111 initialization

[plasmaphase]

lan91c111

I am attempting a full VHDL based driver for the lan91c111 part. I've gotten pretty far along and have written a state machine to read/write registers. As I progress through the initialization requirements of the part, I realized that I have to "emulate" SPI through a register (Bank 3, Offset 8). I found the driver for this part written in c code, and found the read and write phy register functions. I wrote VHDL based on this code, but am unable to read registers (and don't really know if I am writing to them because of my inability to read). The c code driver basically builds an array with the appropriate MDO and MDOE bits, then clocks them out at the end of the function. This clock out process is shown below:

    // Clock all 64 cycles
    for (i = 0; i < sizeof(bits); ++i)
        {
        // Clock Low - output data
        e->bank_3.np_mgmt = mii_reg | bits[i];
        sft_loop_delay(1);

        // Clock Hi - input data
        e->bank_3.np_mgmt = mii_reg | bits[i] | MII_MCLK;
        sft_loop_delay(1);
        bits[i] |= e->bank_3.np_mgmt & MII_MDI;
        }

I've checked my clock rates and think I'm reading/writing slow enough. I am running at 40 MHz and have divided that down by 4096...so I have a counter that counts up to this value, then does a read or write, then resets the counter. When I read the registers, I see that the MDI and MDO bits are both high. I have a pretty detailed understanding of this part and of the spec, so if anyone has any suggestions, no matter how specific, I'm sure I'll be able to pick it up.

Just for reference, below are the steps I take for initialization:

1: powerup chip
2: wait 1 sec (yes, it's overkill)
3: Software Reset (0x8000 to bank 0, offset 4)
4: Software Reset back to 0 (0x0000 to bank 0, offset 4)
5: wait 1 sec (yes, overkill again)
6: Set EPH Power EN bit (0xA0B1 to bank 1, offset 0)

*this is the point in which I attempt to interface via SPI interface (bank 3, offset 8)*

7: MII reset (0x8000 to control register in phy registers)
8: read all the registers to see what's in them (doesn't work)


Please feel free to throw ideas my way or provide any suggestions. Thanks in advance!!

 

[lucbra]

vhdl lan91c111

I've used the LAN9118 recently on a DSP (Tigershark)
I recommend looking at the C-code from the SMSC website. There search for the Init() function.

Are you using chipscope or similar to look at the signals?
I'm afraid it's not obvious to design the interface entirely in VHDL


Regards

 

[plasmaphase]

I've been using signaltap, which is altera's embedded signal "scope" to look at signals. I agree with you that it's not obvious, but if the spec is accurate (which I've already found slight discrepancies between spec and driver c code) it shouldn't be crazy. I'll continue to look at the driver code.

Did this LAN9118 have a spi interface at all? If so, what speed did you read/write to it at? Thank for your reply lucbra. If you have any other suggestions please let me know.

 

[lucbra]

lan91c111 init

Hi,
Sorry it took some time to answer...
I'm debugging a board with Cyclone2, Nios2 and IEEE1588 (precision time protocol), and it it's a bit 'unwilling to cooperate'.

To answer your questions:
Good that you are using signaltap
the LAN9118 didn't have an SPI interface because it's a MAC+PHY device.

I'm not sure if I can give you some immediate suggestions.

Oh, I see one: if both MDO and MDI are high, you should absolutely use an OutEnable signal. Give priority on the out side..
I mean, first write something to the PHY, afterwards, check the busy flags, read the MDI. Make decisions what to do with the received information. But as I mentioned before, it's a hell of a job to write this state machine. I wouldn't start with it...

Just give a shout if you need some help... you can share your code with me if you want. I can check functionality (free of charge of course)
Best regards

 

[plasmaphase]

lan91c111 registers

I ended up getting the initialization of the part working and have it setup to auto-negotiate. There were a few problems, one being endianness. I am able to transmit packets, but am finding that there are "jumbled" packets being sent out in between good packets. I'm not sure if I'm doing everything in the right order, but I've strayed slightly from the c-code driver I'm referencing. It allocates one packet and never de-allocates it nor make additional allocations. Just a 2k byte chunk it uses over and over. I, however, would like to use the auto release feature and have the ability to allocate and de-allocate as I please. I think somewhere in this path I've failed to conform to the order of events. Currently, I am doing the following:

1.) clear interrupt register
2.) allocate packet
3.) poll to check if allocation worked
4.) read assigned packet number
5.) write packet number to packet number register
6.) set auto-increment bit in pointer register
7.) write status word to data register
8.) write packet size to data register
9.) write destination & source mac to data register
10.) write the rest of the data portion of the packet to data register
11.) write control byte and odd byte (if it exists) to data register
12.) turn transmit on (tcr register)
13.) queue packet (mmu comm register)
14.) poll interrupt register for complete *not sure which bit to poll for complete*?
15.) set read for reading status
16.) read data register to check status of transmit
17.) if good, start back at step 5 for next packet?

If anyone has suggestions or sees problems, please feel free to let me know, thank you in advance.

 

[hamed_sotoudi]

lan91c111 reference design

Hi,
I have a problem with lan91c111. I connected it to lx100 fpga. I wrote vhdl code to initialize it. but I don't get any responce from it. I am working in async mode. I wrote very simple code to test it and for start tried to read from its 0x0e register but I read 0xFF from it. can you help me?

 

[itilimited]

We are using LAN91C111 in our design. The initialization of this IC is done through the NIOS II processor in Altera Cyclone III Fpga. We are able to read and write MAC registers of this IC. But when we are trying to read the internal PHY registers, we are always getting 0x0000. I think, even the writting of registers is also not happening. We have done everything as per the application note.But still no progress. Can anyone help me to initialize the internal PHY .... Thanx in advance......

This is the sequence we have done in the code......

1: powerup chip
2: wait 1 sec
3: Software Reset (0x8000 to bank 0, offset 4)
4: Software Reset back to 0 (0x0000 to bank 0, offset 4)
5: wait 1 sec
6: Set EPH Power EN bit (0xA0B1 to bank 1, offset 0)


set bank 3, offset 8

7: MII reset (0x8000 to control register in phy registers)
8: read all the registers to see what's in them (doesn't work)