George_P
Member level 2
Hi,
is there a way to constrain DC to keep all the signal names from RTL to netlist (the ones that are not removed during synthesis) ? I am particularly interested in combinational outputs.
The purpose is to facilitate gate level simulations debugging. Currently, I can only find registers output names. All the combinational outputs get instance-names like "U3432" in the verilog netlist. This makes debugging long combinational paths practically impossible.
Regards,
George
is there a way to constrain DC to keep all the signal names from RTL to netlist (the ones that are not removed during synthesis) ? I am particularly interested in combinational outputs.
The purpose is to facilitate gate level simulations debugging. Currently, I can only find registers output names. All the combinational outputs get instance-names like "U3432" in the verilog netlist. This makes debugging long combinational paths practically impossible.
Regards,
George
