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K-map for synchronous 4-bit decade counter

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May 8, 2011
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I'm a bit at a loss here for a particular assignment we got for one of our labs. I've been using a certain method to derive the k-maps for some circuits, but for this particular one, it didn't really work out too well for some reason. We built and implemented a 4-bit synchronous decade counter. We were then told to make a state diagram, next-state table and a k-map for all the j-k inputs. I'm having a particular issue with the K4/J4 and the K2 maps.

Let me first give you a link to the actual circuit:

**broken link removed**

This is how far I've gotten, I've make a flip-flop transition table, next-state table and also been determining which cells to map with what from it.

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Is there a flaw in my reasoning? For example, I first take Q1, and check the position 0000 against the next state. I then derive what to place in that position for J1 and K1, and I do the following for all the other positions and Q2-Q4. Am I using the wrong method, or have I mapped something wrong or written something wrong?

Here's how far I've gotten:
**broken link removed**

2. Relevant equations
J1/K1 should always be high, which is correct.
J2/K2 should be Q1Q4'. The J2 is correct, but the K2 is not.
J3/K3 should be Q1Q2, which is correct.
J4/K4 should be Q1Q2Q3 + Q1Q4. I however, get some other results.

Where am I wrong in my reasoning? I know there's another way to solve the K-maps for this counter, by checking previous outputs when the current output toggles, but I've used this method before, and it has worked just fine. Am I marking the positions on the K-map wrong or am I using the wrong method, or does it not apply to these, or what?

I'm grateful for any help.

---------- Post added at 13:32 ---------- Previous post was at 12:49 ----------

I noticed some of the expressions on the K-map was wrong, but it didn't change the outcome. Also, the link to the actual circuit might not work for everyone, so here's a working one: **broken link removed**

Here's my current progress: **broken link removed**
Last edited:

If the method of designing is not insisted, there's a tricky way.

You have 10 states. So make a 10 state simple counter (any counter; states must be unique and descrete; say an incrementing counter). Then convert each state into the outputs you wish by a combinational logic. So circuit become structured and easy to debug.

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