quietfoot,
The approaches suggested by matbob and sheikhalipour will work. However, using the asynchronous set and clear inputs suggested by matbob has a potential problem: Suppose in going from states 0111 to 1000, th 2nd LSB bit (2^1) is slightly slower in switching than bits 2^0, 2^2 and 2^3. In this case, the counter would momentarily go to the state 1010, possibly causing a reset to state 0010. I t would be safer to decode state 1001, and use flip flops with synchronous set and clear inputs. This way any momentary false states would be ignored, since they would go away before the next clock pulse. This is the classic "Race" problem.
Regards,
Kral