Jittered clock generating with CADENCE analoglib components

[AdvaRes]

Hi all,

How to generate a jiitered clock signal using analoglib vpulse (or vsin) ?
I need such a signal to determine the maximum jitter supported by the flip flops.

Is there another techniques to determine this maximum jitter supported.

Thanks in advance.
Cheers,
Advares.

 

[erikl]

Re: Jittered clock generating with CADENCE analoglib compone

How to generate a jiitered clock signal using analoglib vpulse (or vsin) ?
I need such a signal to determine the maximum jitter supported by the flip flops.

Hi again, AdvaRes,
You could add 2 vpulse (or vsin) sources with different frequencies as close as you want your frequency jitter.

Is there another techniques to determine this maximum jitter supported.

I think on 15-Feb-09 I sent you the Cadence's VCO_workshop_instruction.pdf . See p. 6 ff there!

Salut, erikl

 

[AdvaRes]

Re: Jittered clock generating with CADENCE analoglib compone

How to generate a jiitered clock signal using analoglib vpulse (or vsin) ?
I need such a signal to determine the maximum jitter supported by the flip flops.

Hi again, AdvaRes,
You could add 2 vpulse (or vsin) sources with different frequencies as close as you want your frequency jitter.

Is there another techniques to determine this maximum jitter supported.

I think on 15-Feb-09 I sent you the Cadence's VCO_workshop_instruction.pdf . See p. 6 ff there!

Salut, erikl

Hi Erikl,

Thanks for replying. If we use 2 sources with differents frequencies there will be a drift with time. I can't see how to get a jitter. Could you please elaborate ?

Yeah sure I got the document regarding the maximum jitter measurment. But my second question was regarding the flip flop. Let me ask the question in another way:
Suppose you have a dff what is the maximum jitter supported by this dff ?
I mean, is there a condition relating peak-to-peak jitter, dff's hold time and setup time that garantees the dff's functionning. (for exemple

peak-to-peak jitter< minimum(hold time, setup time)
or
peak-to-peak jitter<(hold time+ setup time)/2
or something like that.

Its a matter of determining the maximum jitter according to the dff timing constrains.

I hope my question is clear.

Thanks again for replying Erikl,
Cheers,
Advares.

 

[erikl]

Re: Jittered clock generating with CADENCE analoglib compone

If we use 2 sources with differents frequencies there will be a drift with time. I can't see how to get a jitter. Could you please elaborate ?

drift with time : What else is jitter? Of course - with 2 different frequencies you get a very regular (reproducible) jitter. If you want more realistic jitter, then add a noise source (e.g. from the ahdlLib). Even this is not quite "real" jitter, because it doesn't include 1/f (flicker or "pink") noise. If you need this, you must use an appropriate behavorial model, or use the flicker noise of a real device (like a current-loaded resistor), which you map via a vcvs. (Don't forget to cut off the DC part, in this case, by a huge C, or better compensate it by an appropriate vdc.)

Suppose you have a dff what is the maximum jitter supported by this dff ?
I mean, is there a condition relating peak-to-peak jitter, dff's hold time and setup time that garantees the dff's functionning. (for exemple peak-to-peak jitter< minimum(hold time, setup time)
or
peak-to-peak jitter<(hold time+ setup time)/2 or something like that.

Its a matter of determining the maximum jitter according to the dff timing constrains.

Cheers, Advares.

This all depends on the construction of the DFF: If you use an ideal (behavorial) model, you won't get any jitter from it (as long as you don't add extra behavorial jitter). From a real DFF, the jitter depends completely on its extrinsic (parasitics & load dependent) and intrinsic (transistor model dependent) asymmetries.

HTH! Cheers, erikl

 

[AdvaRes]

Re: Jittered clock generating with CADENCE analoglib compone

If we use 2 sources with differents frequencies there will be a drift with time. I can't see how to get a jitter. Could you please elaborate ?

drift with time : What else is jitter? Of course - with 2 different frequencies you get a very regular (reproducible) jitter. If you want more realistic jitter, then add a noise source (e.g. from the ahdlLib). Even this is not quite "real" jitter, because it doesn't include 1/f (flicker or "pink") noise. If you need this, you must use an appropriate behavorial model, or use the flicker noise of a real device (like a current-loaded resistor), which you map via a vcvs. (Don't forget to cut off the DC part, in this case, by a huge C, or better compensate it by an appropriate vdc.)

Suppose you have a dff what is the maximum jitter supported by this dff ?
I mean, is there a condition relating peak-to-peak jitter, dff's hold time and setup time that garantees the dff's functionning. (for exemple peak-to-peak jitter< minimum(hold time, setup time)
or
peak-to-peak jitter<(hold time+ setup time)/2 or something like that.

Its a matter of determining the maximum jitter according to the dff timing constrains.

Cheers, Advares.

This all depends on the construction of the DFF: If you use an ideal (behavorial) model, you won't get any jitter from it (as long as you don't add extra behavorial jitter). From a real DFF, the jitter depends completely on its extrinsic (parasitics & load dependent) and intrinsic (transistor model dependent) asymmetries.

HTH! Cheers, erikl

Thanks Erik,

In the figure below consider the signal 1 (the perfect signal) and signal 2. If I add the two signal I'll get a signal with a variable frequency.
The wanted signal is a signal with the same frequency as signal 1 (the jittered signal in the figure).

 

[erikl]

Re: Jittered clock generating with CADENCE analoglib compone

In the figure below consider the signal 1 (the perfect signal) and signal 2. If I add the two signal ...

You didn't add. You did a logical OR. But that is another story.

... I'll get a signal with a variable frequency.

Again: What else is jitter? The difference is just in size. You call it jitter, if the variation is in the range of ppm's ... %'s (and if it's random, not repetitive), and then you mostly don't call it frequency jitter, but phase jitter. This is just a matter of expression, how you want it to be presented - actually it's the same.

The wanted signal is a signal with the same frequency as signal 1 (the jittered signal in the figure).

Exactly this is produced by a VCO with a somewhat noisy control voltage - and the Cadence workshop shows how it can be measured. I cannot understand why you might want to feed a jitter signal into a VCO, which generates its own jitter? Of course this could be done, easily, if you feed back the (filtered) VCO output to its input (actually, a similar mechanism is used in a PLL) - or by using a 2nd VCO, but why?

 

[AdvaRes]

Re: Jittered clock generating with CADENCE analoglib compone

Hi Erikl,

You didn't add. You did a logical OR. But that is another story.

Please pardon my ignorance, what do you mean by add ?

Exactly this is produced by a VCO with a somewhat noisy control voltage - and the Cadence workshop shows how it can be measured. I cannot understand why you might want to feed a jitter signal into a VCO, which generates its own jitter? Of course this could be done, easily, if you feed back the (filtered) VCO output to its input (actually, a similar mechanism is used in a PLL) - or by using a 2nd VCO, but why?

Let me explain.
Actually I'm using the vpulse element to generate the clock signal for a digital circuit. I wanna simulate this circuit using a jittered clock signal and verify that the circuit works well. Also, I wanna determine the pp (peak to peak) jitter that over which the circuit doesn't work correctly.
Sure a PLL/VCO has a jitter, but you know I have no control on pp jitter. My experiment consist in increasing the pp jitter progressivly till getting errornous result by the circuit. At that time I can say that my circuit support a clock uncertanty=jitter_in_second/clock_periode of, for exemple 10%.

 

[erikl]

Re: Jittered clock generating with CADENCE analoglib compone

... what do you mean by add ?

Algebraic addition. Putting voltage sources in series, or current sources in parallel.

Let me explain.
Actually I'm using the vpulse element to generate the clock signal for a digital circuit. I wanna simulate this circuit using a jittered clock signal and verify that the circuit works well. Also, I wanna determine the pp (peak to peak) jitter that over which the circuit doesn't work correctly.
Sure a PLL/VCO has a jitter, but you know I have no control on pp jitter.

Sure you have; I already told you on Wed, 15 Apr 2009 13:03. Put a noise voltage source in series with a VCO's control voltage source.

My experiment consist in increasing the pp jitter progressivly till getting errornous result by the circuit. At that time I can say that my circuit support a clock uncertanty=jitter_in_second/clock_periode of, for exemple 10%.

In order to achieve this, you progressively increase the value of your noise source (conf. above) - thus the VCO's output jitter - until your follower circuit gives up.