sreevenkjan
Full Member level 5
Hi Guys,
I have a general question regarding Jitter issues and problems. The old circuit consisted of a 25Mhz crystal clock oscillator. The 25Mhz clk was increased to 125Mhz clk and given to the transmitter of the FPGA. However there are jitter issues in the circuit and the jitter needs to be lesser than the reference value.
The solution which I suggested/decided was to use a 125Mhz LVDS clk and give it as input directly to the transmitter of the fpga. I decided on this solution because I read that PLL add on some jitter to the already input jitter. So the LVDS Osci has a jitter of about 0.1ps and crystal clock osci has jitter of 0.3ps.
My question is will my approach help in reducing jitter??
regards,
Sreeni
I have a general question regarding Jitter issues and problems. The old circuit consisted of a 25Mhz crystal clock oscillator. The 25Mhz clk was increased to 125Mhz clk and given to the transmitter of the FPGA. However there are jitter issues in the circuit and the jitter needs to be lesser than the reference value.
The solution which I suggested/decided was to use a 125Mhz LVDS clk and give it as input directly to the transmitter of the fpga. I decided on this solution because I read that PLL add on some jitter to the already input jitter. So the LVDS Osci has a jitter of about 0.1ps and crystal clock osci has jitter of 0.3ps.
My question is will my approach help in reducing jitter??
regards,
Sreeni