What do you mean "the jitter needs to be lesser than the reference value." What's the reference value? Do you mean the 25MHz clock? There are devices called "jitter cleaners" that might be what you want-they are basically PLLs with very narrow filters. Look at TI, IDT, etc.
Is your proposal to use two synchronous clocks? If they're not synchronous, you're going to need to deal with clock-domain-crossing issues.
I presume, yes. Creative circuit design required. E.g. combinations of fast digital logic and variable analog delay.1. Is there a way to measure jitter in the circuit without using a powerful and expensive oscilloscope??
Hi,
1. Is there a way to measure jitter in the circuit without using a powerful and expensive oscilloscope??
Yes, use a powerful and even-more-expensive spectrum analyzer, like tgzzz suggests.1. Is there a way to measure jitter in the circuit without using a powerful and expensive oscilloscope??
You still haven't told us what your target jitter is, or what the jitter from your old method was, so we can't really say whether a given solution will work or not.
Using an external PLL+VCO instead of the ones integrated in the FPGA should surely improve your results, sure, but beyond that we need more info.
Hi,
I have mentioned the target jitter in my messages earlier. Target jitter is 25ps and the measured jitter is about 40ps. What more info do you want??
regards,
Sreeni
This says to everyone else (that isn't inside your head) that you have a reference clock with 25ps jitter, but the clock you are generating based on that reference has 30-40ps of jitter (which is actually pretty good, only adding 15ps of jitter).Thank you for the answer. Well when I say reference value, it is the threshold value. I mean if the reference value is 25ps then my jitter measured is about 40ps or 30ps.
It's said in FPGA datasheet that the internal PLL operated in low bandwidth mode can be used to reduce clock jitter. But that's only true for very bad input clocks. Surely not for 25 ps jitter. In most cases, the FPGA clock networks and particularly the PLLs will increase jitter.
How did u obtain the diagram where you are able to calculate the Jitter outputted for a particular input frequency??
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