Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

jitter generation circuit

Status
Not open for further replies.

Rainbow00

Junior Member level 3
Joined
Feb 23, 2006
Messages
29
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,504
Hi,

i need a tunable jitter generation circuit to test the jitter tolearance circuit for a PLL. the PLL can take 19.2MHz, 26MHz and 60MHz clocks. it is prefered that the jitter can be turned up to 2ns.

i did build one circuit with 74 series XOR gate on a breadboard, which takes the clock from waveform generator. however, the clock output suffers from stability problem. assuming i have access to breadboard, waveform generator and common components.

regards
gd
 

hi

mm quite interesting requirement since jitter is assumed to be already present in any kind of circuit.

Sal
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top