jaishankar
Junior Member level 2
Hi,
I've synthesised individual modules in a microprocessor design. (with individual verilog modules.. like for alu, memory, etc.) All were working fine; in fact each of them were synthesised within a span of 60 seconds.
But, when I put it together it doesn't happen fast. I've run the software for about a one hour, the terminal shows -"sent 'cu' to server"
NOte: 'cu' is the top module in my design - cu is the control unit.
I think it is stuck with this module.. -> the gui status bar reads "computing design state".
Does it usually take this long to synthesise a simple single cycle microprocessor?
i'm using .. these verilog codes/ in this link -> https://thelinuxmaniac.files.wordpress.com/2010/11/code.pdf
I've synthesised individual modules in a microprocessor design. (with individual verilog modules.. like for alu, memory, etc.) All were working fine; in fact each of them were synthesised within a span of 60 seconds.
But, when I put it together it doesn't happen fast. I've run the software for about a one hour, the terminal shows -"sent 'cu' to server"
NOte: 'cu' is the top module in my design - cu is the control unit.
I think it is stuck with this module.. -> the gui status bar reads "computing design state".
Does it usually take this long to synthesise a simple single cycle microprocessor?
i'm using .. these verilog codes/ in this link -> https://thelinuxmaniac.files.wordpress.com/2010/11/code.pdf