Issues with DC and RTI files with include construct

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jitendra

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DC issue

Hi,
Can anybody help me in following issue?
I am using DC for verilog design. Some RTl files have 'include construct.
So when I analyze such files, DC searches for the included file in search_path but the included file is in design directory. So DC is unable to read this file. Actually I am analyzing the included file before reading the top file But DC is still trying to locate these files and issuing error.
Let me know work around for this.

Thanks,
Jitendra
 

Re: DC issue

Maybe you can try your scripts like this : read_verilog {include.v main.v};
I just used this method in combine multifiles.
 

Re: DC issue

May be you can give design directory in the search path, so that DC will search for the include files in the design directory as they are located there.
 

Re: DC issue

check the path of the file wrt your DC run dir.
 

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