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[SOLVED] Issues Of 1.5-bit Stage Design

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Junior Member level 2
Aug 5, 2014
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We know that there are three situation of Sub-Adc for this title
State 1) Vin>+Vref/4
State 2) Vin<-Vref/4
State 3) -Vref/4<Vin<+Vref/4
Also using dynamic comparator is most common, I've design that too
Additionally, we know that if Vin+ - Vin- > Vref+ - Vref- (Vin+>+Vref/4 and Vin-<-Vref/4 subsequently) Vop of comparator is 1 and the other one is 0 and it'll be inverse vice versa.
I have two questions about this part and I'll present my other issues later, I would be appreciate if you answer my clear simple questions please.

First Question:
I think I can't make it work for the state 3 by only comparator because states 2 and 3 have similar results; Vop=0, Von=1. I've realized I may implement the function using two dynamic comparators. let me know if I'm wrong and tell me how to do that in details please.

Second Question:
When Vout+ and Vout- of S/H of first stage have common mode,we can add that common mode to the thresholds of comparators, is this a good way or we should use a common mode cancellation circuit, would you please describe the issue of common mode presence too.
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in the continue.. I have an issue in the design of MDAC
OTA is good enough for my requirements,it has more than 110 dB gain and 500MHz UGB (CMFB ADDED)
I've used an flip around S/H before first stage at the beginning,
I've used BS switch (well designed) to charge Sampling and Feedback capacitors of MDAC and I've used a CMOS switch for holding mode of MDAC.

in this case diff input is 0.3v but output of MDAC is more than 0.6v gain is more than 2 also it seems rising kind of stability issue.. would anyone please have some concern on solving this complication :?:
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I've solved my problem here and I just sharing it now, I've worked on switches, all switches must be CMOS switch or BS switch (working on 90nm tech).
Good Luck.

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