Firstly i'd like to know the difference between the following modes:
(Im referring to the Xilinx XST userguide)
1.) Read first
2.) Write first
3.) No change..
Secondly, in the following code (No change mode)
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity rams_03 is
port (clk : in std_logic;
we : in std_logic;
en : in std_logic;
addr : in std_logic_vector(5 downto 0);
di : in std_logic_vector(15 downto 0);
do : out std_logic_vector(15 downto 0));
end rams_03;
architecture syn of rams_03 is
type ram_type is array (63 downto 0) of std_logic_vector (15 downto 0);
signal RAM : ram_type;
begin
process (clk)
begin
if clk'event and clk = '1' then
if en = '1' then
if we = '1' then
RAM(conv_integer(addr)) <= di;
else
do <= RAM( conv_integer(addr));
end if;
end if;
end if;
end process;
end syn;
a.) why is ram_type defined as a "signal". wouldnt a "variable" do just fine or mebbe better since there are no delays associated with it.
b.) why are input and output ports seperate. Isnt ram supposed to have a single data bus ? Further will the multiple driver resolution problem arise if i declare the data bus as INOUT.
Dear Nikolai
Why do you want to declare RAM as an variable? A signal over there is perfectly fine. Variable may cause a problem, and moreover you will have to map the variable then ultimately to a signal, because variables are temporary storage, and cannot be used to retain the data.
RAMs MAY have a single bus for RD/WR, but its not that RAM WILL have that, also most RAMs today have different RD and Write buses. INOUT are only used to drive signals off chip. Anything inside the chip generally will not be of INOUT type.
But if you want you can delcare a signal signal with inout type, and use tristate buffers with them. A correct use of tristate buffers will prevent multiple drivers issue on it.
Kr,
Avi http://www.vlsiip.com
there is no such a think as biderectional buses inside FPGA, even if you declare bi-directional signal inside your module compiler will have to create two separate busses.
Also there are no tri-state buffers inside FPGA better practice is to use multiplexor, again if you are puting tri-stable buffer complier will put MUX.
Bottom line is why do we need to create additional job for complier?
I agree, but suppose if my processor had a single port and a ram is to be interfaced to it, in that case there is no room for two seperate Din and Dout buses.
You mean BIDIRECTIONAL DATA BUS on cpu? in this case ouput buffers from FPGA does have capabilty of tri-state buffers on pins only, you will need external signal to control tri-state buffers it can be read from CPU with additional address decoder logic
just to make it more clear, my processor and the RAM both will reside inside the FPGA
i.e im implementing a processor and a ram inside the FPGA and interfacing them internally...
If processor and ram is to be implemented in a same fpga then why dont u go for separate bus it self as it will definately get implemented by compiler.
Most FPGA CPU's have separate ports for read data and write data.
Most FPGA RAM's have dual ports.
That eliminates the need for an internal bidirectional data bus.