DarkInsanePyro
Newbie level 5
So I am having an issue wrapping my head around VHDL and lately been beating my head against a snippet I have made. I will be straight out with you this is an assignment for my class, but I am not asking for a solution, just for some help. I seem to be missing how my code is being synthesized and why my functions are not operating as expected. I surfed around trying to get an idea of the various constructs that VHDL gives us, but I may be missing something in this case. This material is rather self-taught and no notes to refer to, so that is off the table. This is purely online research and my own development. I am familiar with Verilog so I am surprised I am having an issue with this language (though it seems to be a lot more generic).
The following is a snippet of my code. I suspect the Add function is not operating the FullAdder properly and I have a feeling I don't understand how the for-loop is being unrolled. So I am hoping and would highly appreciate any assistance on what oversight I seem to have fallen victim to.
The following is a snippet of my code. I suspect the Add function is not operating the FullAdder properly and I have a feeling I don't understand how the for-loop is being unrolled. So I am hoping and would highly appreciate any assistance on what oversight I seem to have fallen victim to.
Code:
function FullAdder(a,b,c : std_logic) return AdderResult is
variable result : AdderResult;
begin
-- calculate the return bit value
result.q := a xor b xor c;
-- calculate if a carry has occured
result.c := (a and b) or (c and (a xor b));
return result;
end;
-- Add
-- adds two logic vectors together and returns a vector one larger than
-- the largest to hold the extra bit of data (carry)
function Add(x,y : std_logic_vector) return std_logic_vector is
variable temp : std_logic_vector(x'high+1 downto 0) := (others => '0');
variable ret : AdderResult;
variable c : std_logic := '0';
begin
-- make sure the input vectors are the same length
assert x'high = y'high report "input vectors must be of equal length (x:" & integer'image(x'high) & ", y:" & integer'image(y'high) & ")";
-- loop through each bit of the vectors and add them together with carry
for n in 0 to x'high loop
ret := FullAdder(x(n), y(n), c); -- add the two bits together with the previous carry
temp(n) := ret.q; -- store the resulting bit in temp (return var)
c := ret.c; -- store the new carry value for the next iteration
end loop;
temp(x'high+1) := c; -- store the last carry flag in the final bit of the result
return temp;
end;