In scan chain always there should be scannable flops. Non scanable flops are connected to output of scannable flops. But as U told there is all non-scannablr flops in scan chain, that means your scan stitiching was done incorrectly. Please check with your scan style, scan mode.
I mean that several non-scan DFF,not all.I want to know why Design Compiler not replace these non-scan DFF with scan DFF,why stitch them in a scan chain?
Did you check the post dft_drc report. Does it have any Warnings?.
Once i encountred this type of issue when i was using DB mode. The reason was some modules are applied set_dont_touch attribute and cells was not replaced as scanalbe cells. check this point if its applicable..
if you have problems in analyzing the warnings,share dft_drc report or warning list in dft_drc with us.dft_drc report will definilty let you know wahts the cause for ur problem...
There are ways to exclude the flops of your interst in DB(set_scan_exclude ..) as well as XG mode (set_scan_config -exclude_elements ).
If you give option set_scan_configuration -insert_shift_registers true then some flops which are one after other without any combo in between will not be scan replaced but this is correct and it will pass simulation.
If you give option set_scan_configuration -insert_shift_registers true then some flops which are one after other without any combo in between will not be scan replaced but this is correct and it will pass simulation.
rudrad is exactly correct - the synthesis tool will use shift registers and other flop stages without combinational logic between as is, without explicit scan replacement, I believe, by default.
I don't know about that 'set_scan_configuration -insert_shift_registers true' - maybe in an old version - but the proper way to do it explicitly these days is a 'set_scan_group' command.
once u done the scan insertion, check the report properly. if non scan cells are stiched with scan cells it means scan stiching not happening properly. check with proper dc commonds