isolated nmos devices simulation and layout

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zitty

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Hello,

I´m using isolated nmos devices in my design. Let´s take an inverter with a normal pmos device on top and a isolated nmos device at bottom as an example.

If I instert the isolated nmos device in my scematic the bulk has two connection.
I assume that one is for the "normal bulk" and I will connect that to gnd. But where do I have to connect the other connection? to the substrate?

Another point is concerning the layout. where do i have to place substrate and well contacts?

can you give me any example?

thanks
 

Hey Zitty....
put up ur circuit for better understanding......
 

ok, to the first problem:
maybe this illustration helps.


Where do I have to connect Terminal1 and Terminal 2?
At the moment I connected Terminal2 to gnd and terminal1 to another substrate potential. Is that correct?
 

I think this isolated nmos is a conventional nmos in a P-Well (bulk connected to Vss), but that P-Well is inside an NWell. This N Well should be connected to Vcc. This means that any noise from the P-Substrate (the normal bulk for non isolated nmos devices) cannot get to the isolated P-Well as there is a reverse biased PN Diode.

 

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