ISO cells in always on logic?

[fail1]

When doing Low Power, why the Isolation cell need to be placed in always-on logic?

Thx
Kumar

 

[YuLongHuang]

The low power technique you means is power-gating.
It is the technique that you can turn off the power supply for specific region within IC.
Here the "turn off" means no power supply instead of inactive state.
For example, you would like to turn off the power supply of arithmetic during sleep mode.

Therefore, the logic can be divided into 1. always-on logic 2. shut-down logic
However, there is data path between these two logic. As the result, we need isolation cell between them.
The purpose of isolation cell is to isolate the unknown signal from shut-down logic to avoid unpredictable output.

For instance, the flip-flop sample the sum of adder which is on shut-down region.
Once the adder is turned off, the sum is unknown or high-impedance since there is no power supply anymore.
Now the flip-flop can't directly sample the sum of adder. This will cause unpredictable result.
To isolate this input, we insert isolation cell by tool automatically. For example, OR gate with power-off active-high signal.

 

[fail1]

Thanks for the reply!

 

[eshwarks]

Hi YuLongHuang,
how isolation cells different from regular AND/OR cells?
can we use regular AND/OR cell as isolation cell ?

thanks in advance

 

[layowblue]

ISO cell is powered by always-on region. It never outputs X value on functional/scan modes.
If you guarantee certain AND/OR gates are always powered, you can use it as certain type of ISO cells. But remember the logic needs to be correct. For example, always-on AND gates could be used as ISO cells for those power-off value output need to be zero(not one).
Fortunately, in current CPF flow, tool will handle the ISO cell insertion based on your input constraint in term of power-off values.

 

[eshwarks]

thanks a lot for the quick response layowblue