nesta
Junior Member level 2

Hi VhdlExperts,
I am using Xilinx webpack 12.4 ISIM and see some strange results for sfixed values especially for negative numbers.
for eg:
signal Ain : sfixed(7 downto -3);
Ain <= to_sfixed(-2.5),Ain);
gives me 11111101100 (ie 11111101.100 ) instead of 11111110.100
-----
Ain <= to_sfixed(-3.5),Ain);
gives me 11111100100 (ie 11111100.100 ) instead of 11111101.100
---
Am i doing something wrong, or my intrepretation is wrong.
Also would like to know if the operators & functions like ( + addition, * mul, abs) are synthesizable as i am using simulator currently.
Please help.
Thanks,
Sunish
I am using Xilinx webpack 12.4 ISIM and see some strange results for sfixed values especially for negative numbers.
for eg:
signal Ain : sfixed(7 downto -3);
Ain <= to_sfixed(-2.5),Ain);
gives me 11111101100 (ie 11111101.100 ) instead of 11111110.100
-----
Ain <= to_sfixed(-3.5),Ain);
gives me 11111100100 (ie 11111100.100 ) instead of 11111101.100
---
Am i doing something wrong, or my intrepretation is wrong.
Also would like to know if the operators & functions like ( + addition, * mul, abs) are synthesizable as i am using simulator currently.
Please help.
Thanks,
Sunish