ISE7.1: Xst:Portability/export/Port_Main.h:127:1.13.276.1

[voho]

fatal error ISE7.1i

Hi all,

When i synthesize my vhdl code with ise7.1i i have this message:

FATAL ERROR:Xstortability/export/Port_Main.h:127:1.13.276.1

Thank's in advance

Regards

 

[Sparc]

Re: fatal error ISE7.1i

Plz be more specific about ur HDL module. I am also using ISE7.1 but haven't yet faced such problem.
Try searching Xilinx Answer Database.

 

[sp]

Re: fatal error ISE7.1i

go xilink website n search for the answer for ur prob..

i searched for u ..... n i found,,,

**broken link removed**

"FATAL_ERROR:Xst:Portability/export/Port_Main.h:127:1.13."

Xilinx is committed to fixing all XST fatal errors and will analyze any problems that you are experiencing in order to improve future versions of XST. Consequently, even if this Answer Record allows you to work around the fatal error, please open a WebCase with Xilinx Customer Support at:
[I]**broken link removed**[/I]

Solution 1:

This fatal error is issued for a variety of reasons. Read the last several items in the synthesis report to see what XST was performing last; if this corresponds to one of the synthesis options, turn that option Off and re-run synthesis. XST might bypass the portion in the synthesis engine that is causing the error. First, be sure that the Advanced Options are turned On in ISE:
1. Select the "Edit" pull-down menu in Project Navigator.
2. Select "Preferences."
3. Select the "Processes" tab.
4. Change the Property Display Level from "Standard" to "Advanced."
5. Click "OK."

To select the synthesis options:
1. Highlight the HDL file that you want to synthesize.
2. Right-click the "Synthesize - XST" process.
3. Select "Properties."

The window that appears contains all synthesis properties that are available from the GUI.

NOTE: The most common switch that seems to resolve some fatal errors is the "shift Register Extraction" in the "HDL Options" tab.

there is lots more sol to ur prob,,,,go the link i gave u n look for urself...


sp

 

[echo47]

fatal error ISE7.1i

I assume that problem occurs in one project, but not all projects. Correct?

When I run into that sort of problem, I begin commenting-out large blocks of my source code until the problem disappears. Then I carefully un-comment-out sections until I locate the offending statement. Could be a syntax error, could be compiler bug.

 

[voho]

Re: fatal error ISE7.1i

Hi all,

Now the synthesize work perfectelly becaus i have doing this in synthesize option:

Register balancing = No

But the Implement Design doesn't work i have this message:

ERROR: PAR failed
Process "Place route" did not complete

Thank's in advance Best regards