pigtwo
Member level 4
Hello everyone!
I'm working on a design using ISE 14.6 and there is something that I don't really understand that ISE is doing. When I start the operation to generate the programming file I get a warning that says the design is too big for the FPGA and when I look in the design results tab the percentage of LUTs used is 118%. Which is fine but it is only like this during the synthensize phase. ISE then happily continues with the last phases and generates a programming file. Then when I look at the design results tab everything is now under 100% but some are very close.
Does ISE just prune the design so that it fits? I tried using the file but it didn't seem to work(unsurprisingly).
What is going on here?
Also while I'm on the subject I also get this warning:
I take this means the design is too large but where is the 153 coming from? Is it suggesting that the design 153% of the available resources? The highest number I can find in the report is 118%.
Thank you!
I'm working on a design using ISE 14.6 and there is something that I don't really understand that ISE is doing. When I start the operation to generate the programming file I get a warning that says the design is too big for the FPGA and when I look in the design results tab the percentage of LUTs used is 118%. Which is fine but it is only like this during the synthensize phase. ISE then happily continues with the last phases and generates a programming file. Then when I look at the design results tab everything is now under 100% but some are very close.
Does ISE just prune the design so that it fits? I tried using the file but it didn't seem to work(unsurprisingly).
What is going on here?
Also while I'm on the subject I also get this warning:
Code:
WARNING:Xst:2254 - Area constraint could not be met for block <LED_Grid>, final ratio is 153.
Thank you!